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CS4391A 24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering 108 dB Dynamic Range 94 dB THD+N Direct Stream Digital Mode Low Clock Jitter Sensitivity +5 V Power Supply ATAPI Mixing On-Chip Digital De-emphasis for 32, 44.1, and 48 kHz Volume Control with Soft Ramp
- 119 dB Attenuation - 1 dB Step Size - Zero Crossing Click-Free Transitions
Description
The CS4391A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4391A accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, consumes very little power and operates over a wide power supply range. These features are ideal for DVD, A/V receivers, CD and set-top box systems. ORDERING INFORMATION CS4391A-KS 20-pin SOIC -10 to 70 C CS4391A-KZ 20-pin TSSOP -10 to 70 C CS4391A-KZZ 20-pin TSSOP, Lead Free -10 to 70 C CDB4391A Evaluation Board
Direct Interface with 5 V to 1.8 V Logic
I
M1 (SDA/CDIN)
M3
M2 (SCL/CCLK)
M0 (AD0/CS)
AMUTEC
BMUTEC
CMOUT
FILT+
MODE SELECT (CONTROL PORT) RST
EXTERNAL MUTE CONTROL
REFERENCE
INTERPOLATION FILTER SCLK SERIAL PORT LRCK INTERPOLATOR FILTER SDATA
VOLUME CONTROL
DAC
ANALOG FILTER
AOUTA+ AOUTA-
MIXER AOUTB+ VOLUME CONTROL DAC ANALOG FILTER AOUTB-
MCLK
Preliminary Product Information
www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
JUL `04 DS600PP3 1
CS4391A
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13 3. REGISTER QUICK REFERENCE .......................................................................................... 15 3.1 Mode Control 1 (address 01h) .......................................................................................... 15 3.2 Volume and Mixing Control (address 02h)........................................................................ 16 3.3 Channel A Volume Control (address 03h) ........................................................................ 16 3.4 Channel B Volume Control (address 04h) ........................................................................ 16 3.5 Mode Control 2 (address 05h) .......................................................................................... 17 4. REGISTER DESCRIPTION .................................................................................................... 18 4.1 Mode Control 1 - Address 01h .......................................................................................... 18 4.1.1 Auto-Mute (Bit 7) ................................................................................................. 18 4.1.2 Digital Interface Formats (Bits 6:4) ...................................................................... 18 4.1.3 De-Emphasis Control (Bits 3:2) ........................................................................... 18 4.1.4 Functional Mode (Bits 1:0) .................................................................................. 18 4.2 Volume and Mixing Control (Address 02h) ....................................................................... 19 4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 19 4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ......................................................... 19 4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ...................................................... 19 4.3 Channel A Volume Control - Address 03h ........................................................................ 19 4.4 Channel B Volume Control - Address 04h ....................................................................... 20 4.4.1 Mute (Bit 7) .......................................................................................................... 20 4.4.2 Volume Control (Bits 6:0) .................................................................................... 20 4.5 Mode Control 2 - Address 05h .......................................................................................... 20 4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................ 20 4.5.2 Control Port Enable (Bit 5) .................................................................................. 20 4.5.3 Power Down (Bit 4) ............................................................................................. 20 4.5.4 AMUTEC = BMUTEC (Bit 3) ............................................................................... 20 4.5.5 Freeze (Bit 2) ...................................................................................................... 21 4.5.6 Master Clock Divide (Bit 1) .................................................................................. 21
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 22 6. PIN DESCRIPTION - DSD MODE .......................................................................................... 26 7. APPLICATIONS ..................................................................................................................... 33 7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 33 7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 33 7.3 Analog Output and Filtering ............................................................................................. 33 8. CONTROL PORT INTERFACE .............................................................................................. 34 8.1 SPI Mode ......................................................................................................................... 34 8.2 I2C Mode ......................................................................................................................... 34 9. PARAMETER DEFINITIONS .................................................................................................. 38 10. REFERENCES ...................................................................................................................... 38 11. PACKAGE DIMENSIONS ................................................................................................. 39
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Modes ................................................................................ 27 Table 2. Digital Interface Formats - DSD Mode................................................................................... 27 Table 3. De-Emphasis Mode Selection .............................................................................................. 27 Table 4. Functional Mode Selection .................................................................................................... 27 Table 5. Soft Cross or Zero Cross Mode Selection ............................................................................ 27 Table 6. ATAPI Decode ....................................................................................................................... 28 Table 7. Digital Volume Control........................................................................................................... 28 Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies................................ 29 Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies ......................... 29 Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies ........................ 29 Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options .............. 29 Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ..................... 29 Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options......... 29 Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ......... 30 Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options ................................................... 30 Table 16. Memory Address Pointer (MAP) .......................................................................................... 35
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LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 9 Figure 2. Direct Stream Digital - Serial Audio Input Timing ........................................................... 10 Figure 3. I2C Control Port Timing .................................................................................................. 11 Figure 4. SPI Control Port Timing ................................................................................................. 12 Figure 5. Typical Connection Diagram - PCM Mode ..................................................................... 13 Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14 Figure 7. Format 0, Left Justified up to 24-Bit Data....................................................................... 31 Figure 8. Format 1, I2S up to 24-Bit Data ..................................................................................... 31 Figure 9. Format 2, Right Justified 16-Bit Data ............................................................................. 31 Figure 10. Format 3, Right Justified 24-Bit Data ........................................................................... 31 Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 32 Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 32 Figure 13. De-Emphasis Curve ..................................................................................................... 32 Figure 14. ATAPI Block Diagram .................................................................................................. 32 Figure 15. CS4391A Output Filter ................................................................................................. 33 Figure 16. Control Port Timing, SPI mode .................................................................................... 35 Figure 17. Control Port Timing, I2C Mode ..................................................................................... 35 Figure 18. Single-Speed Frequency Response ............................................................................ 36 Figure 19. Single-Speed Transition Band ..................................................................................... 36 Figure 20. Single-Speed Transition Band ..................................................................................... 36 Figure 21. Single-Speed Stopband Rejection ............................................................................... 36 Figure 22. Double-Speed Frequency Response ........................................................................... 36 Figure 23. Double-Speed Transition Band .................................................................................... 36 Figure 24. Double-Speed Transition Band .................................................................................... 37 Figure 25. Double-Speed Stopband Rejection .............................................................................. 37
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1. CHARACTERISTICS/SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25 C, VA = 5.0 V)
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters DC Power Supply Specified Temperature Range Symbol VA VL -KS & -KZ TA Min 4.75 1.8 -10 Typ 5.0 Max 5.25 VA 70 Units V V C
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 6.0 VA 10 VL+0.4 125 150 Units V V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; Test load RL = 5 k, CL = 10 pF) VA = 5 V Parameter Dynamic Performance Dynamic Range (Note 1) unweighted A-Weighted A-Weighted (Note 1,2) THD+N 0 dB -20 dB -60 dB (1 kHz) normal operation power-down state normal operation power-down Power Supply Rejection Ratio (1 kHz) (Note 3) PSRR (60 Hz) Symbol Min 1.05VA 5 IA + IL IA + IL 100 103 Typ 1.1VA 0.43VA 0.1 100 105 108 102 -94 -85 -45 108 100 17 60 85 0.3 60 40 Max 1.15VA 100 -89 -40 35 175 dB dB dB dB dB dB dB dB mA A mW mW dB dB Units Vpp VDC dB ppm/C k pF Symbol Min Typ Max Unit
40 kHz Bandwidth Total Harmonic Distortion + Noise
Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Power Supplies Power Supply Current Power Dissipation
Parameter Analog Output Full Scale Differential Output Voltage Common Mode Voltage Interchannel Gain Mismatch Gain Drift AC-Load Resistance Load Capacitance
CMOUT
RL CL
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ANALOG CHARACTERISTICS (continued)
Parameter Symbol Min Typ Max Combined Digital and On-chip Analog Filter Response - Single Speed Mode Passband (Note 3) to -0.05 dB corner 0 .4535 to -3 dB corner 0 .4998 Frequency Response 10 Hz to 20 kHz -.02 +.035 StopBand .5465 StopBand Attenuation (Note 5) 50 Group Delay tgd 9/Fs Passband Group Delay Deviation 0 - 20 kHz 0.36/Fs De-emphasis Error (Relative to 1 kHz) Control Port Mode Fs = 32 kHz +.2/-.1 Fs = 44.1 kHz +.05/-.14 Fs = 48 kHz +0/.22 Stand-Alone Mode Fs = 44.1 kHz +.05/-.14 Combined Digital and On-chip Analog Filter Response - Double Speed Mode Passband (Note 4) to -0.1 dB corner 0 .4621 to -3 dB corner 0 .4982 Frequency Response 10 Hz to 20 kHz -0.1 0 StopBand .577 StopBand Attenuation (Note 5) 55 Group Delay tgd 9/Fs Passband Group Delay Deviation 0 - 20 kHz 0.23/Fs On-chip Analog Filter Response - Quad Speed Mode Passband (Note 4) to -3 dB corner 0 0.25 Frequency Response 10 Hz to 20 kHz -0.7 0 On-chip Analog Filter Response - DSD Mode Passband (Note 4) to -3 dB corner 0 1.0 Frequency Response 10 Hz to 20 kHz -0.7 0 Notes: 1. 2. Triangular PDF dithered data. THD+N specifications for 48 kHz sample rates are made over a 20 kHz Bandwidth. Unit
Fs Fs dB Fs dB s s dB dB dB dB
Fs Fs dB Fs dB s s
Fs dB
Fs dB
3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing the capacitance will also increase the PSRR. 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 18-25) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
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DIGITAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.)
Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current Symbol VIH VIL Iin Min 70% Typ 8 3 Max 20% 10 Units VL VL A pF mA
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SWITCHING CHARACTERISTICS - PCM MODES
Parameters Input Sample Rate LRCK Duty Cycle MCLK Duty Cycle SCLK Frequency SCLK Frequency SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time (Note 6) tslrd tslrs tsdlrs tsdh Symbol Fs 4 45 40 20 20 20 20 (Inputs: Logic 0 = 0 V, Logic 1 = VL) Typ 50 50 Max 200 55 60 MCLK/2 MCLK/4 Units kHz % % Hz Hz ns ns ns ns
Min
Notes: 6. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
LRCK
t s lrd
t slrs
S C LK
t s d lrs
S D AT A
t sdh
Figure 1. Serial Mode Input Timing
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SWITCHING CHARACTERISTICS - DSD
Parameter MCLK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsclkl tsclkh tsclkw tsdlrs tsdh (Logic 0 = AGND = DGND; Logic 1 = VL) Symbol Min 40 20 20 20 20 20 Typ 50 Max 60 Unit % ns ns ns ns ns
t sclkh t sclkl S C LK t s dlrs t sd h
S D A TA
Figure 2. Direct Stream Digital - Serial Audio Input Timing
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SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs:
logic 1 = VL) Parameter I C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition (Note 7) fscl tirs tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 100 1 300 KHz ns s s s s s s ns s ns s
2(R)
logic 0 = AGND, Max Unit
Symbol
Min
Notes: 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST t irs R ep ea ted S ta rt
Stop
SDA
Start
Stop
t buf
SC L
t hdst
t high
t
hdst
tf
t susp
t
lo w
t
hdd
t sud
t sust
tr
Figure 3. I2C Control Port Timing
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SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs:
logic 1 = VL) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 9) (Note 10) (Note 10) (Note 8) fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 500 500 1.0 20 66 66 40 15 6 100 100 MHz ns ns s ns ns ns ns ns ns ns Symbol Min Max Unit logic 0 = AGND,
Notes: 8. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 9. Data must be held for sufficient time to bridge the transition time of CCLK. 10. For FSCK < 1 MHz
RST
t srs
CS t spi CCLK t css t scl t sch t csh
t r2
C D IN
t f2
t ds u t dh
Figure 4. SPI Control Port Timing
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2. TYPICAL CONNECTION DIAGRAMS
0.1 f
+ 1.0 f
+5V Analog
10 Mode S elect
(Control Port) *
17 VA
M 0 (A D 0/C S ) M 1 (S DA /C D IN )
9
8 7
M2 (SCL/CCLK) M3
FILT+ 11
0.1 f
+ 1.0 f
C S4 391A
Logic Power +5V to 1.8V
2 0.1 f VL
A OU T A-
19 A na log C onditioning & M ute
AMUTEC 20 5
LR CK
A O UT A + 18
Au dio D ata P ro cessor *
4 3
S C LK S D AT A A OU T B14 A na log C onditioning & M ute
1
BM U T EC 13
RST
AO U TB + 15
6
M C LK
CMOUT 12
AG N D 16
+ 1.0 f
E xternal C lock
Figure 5. Typical Connection Diagram - PCM Mode * A high logic level for all digital inputs should not exceed VL.
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0.1 f 17 VA 10 M o de S e le ct
(Control Port)
+1.0 f
+5V Analog
M 0 (A D0 /C S ) M 1 (S D A/C DIN ) M 2 (SC L /C C LK ) FILT +
9 8
11 0.1 f
+ 1.0 f
CS4391A
Lo gic Pow e r +5V to 1.8V 2 0.1 f
5
A OU T AVL
DSD_MODE
19 A na lo g C on d itionin g & M ute
AMUTEC 20 A O UT A + 1 8
7 A u dio D ata P ro ce ssor * 4 3 1 6
D SD _ C LK
D SD _B
A OU T BD S D _A B M U TE C 1 3 RST M CL K AG N D 16 A OUTB+ 15 14 A na log C on d ition in g & M u te
CMOUT 1 2 + 1.0 f
E xtern al C lo ck
Figure 6. Typical Connection Diagram - DSD Mode * A high logic level for all digital inputs should not exceed VL.
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3. REGISTER QUICK REFERENCE
** "default" ==> bit status after power-up-sequence or reset**
3.1
MODE CONTROL 1 (ADDRESS 01H)
7 AMUTE 1 6 DIF2 0 5 DIF1 0 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0
AMUTE (Auto-mute) Default = `1'. 0 - Disabled 1 - Enabled DIF2, DIF1 and DIF0 (Digital Interface Format - PCM Modes). See Table 1 Default = `0'. 000 - Format 0, Left Justified, up to 24-bit data 001 - Format 1, I2S, up to 24-bit data 010 - Format 2, Right Justified, 16-bit Data 011 - Format 3, Right Justified, 24-bit Data 100 - Format 4, Right Justified, 20-bit Data 101 - Format 5, Right Justified, 18-bit Data 110 - Reserved 111 - Reserved DIF2, DIF1 and DIF0 (Digital Interface Format - DSD Mode Only). SeeTable 2 Default = `0'. 000 - Format 0, 64x oversampled DSD data with a 4x MCLK to DSD data rate 001 - Format 1, 64x oversampled DSD data with a 6x MCLK to DSD data rate 010 - Format 2, 64x oversampled DSD data with a 8x MCLK to DSD data rate 011 - Format 3, 64x oversampled DSD data with a 12x MCLK to DSD data rate 100 - Format 4, 128x oversampled DSD data with a 2x MCLK to DSD data rate 101 - Format 5, 128x oversampled DSD data with a 3x MCLK to DSD data rate 110 - Format 6, 128x oversampled DSD data with a 4x MCLK to DSD data rate 111 - Format 7, 128x oversampled DSD data with a 6x MCLK to DSD data rate DEM1, DEM0 (De-Emphasis Mode). See Table 3 Default = `00'. 00 - No De-emphasis 01 - 44.1 kHz De-Emphasis 10 - 48 kHz De-Emphasis 11 - 32 kHz De-Emphasis FM1, FM0 (Functional Mode). See Table 4 Default = `00'. 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode
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3.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)
7 A=B 0 6 Soft 1 5 Zero Cross 0 4 ATAPI4 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1
A = B (Channel A Volume = Channel B Volume)
Default = `0'. 0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by register 04h. 1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ignored.
Soft & Zero Cross (Soft control and zero cross detection control)
Default = `10'. SoftZero CrossMode 00 Changes take effect immediately 01 Changes take effect on zero crossings 10 Changes take effect with a soft ramp (default) 11 Changes take effect in 1/8 dB steps on each zero crossing
ATAPI 0-4 (Channel mixing and muting). SeeTable 6 Default = `01001', (Stereo) AOUTA = Left Channel AOUTB = Right Channel 3.3 CHANNEL A VOLUME CONTROL (ADDRESS 03H)
See Channel B Volume Control (address 04h)
3.4
CHANNEL B VOLUME CONTROL (ADDRESS 04H)
7 MUTE 0 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0
MUTE Default = `0' 0 - Disabled 1 - Enabled Volume Default = `0' (Refer to Table 7)
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3.5 MODE CONTROL 2 (ADDRESS 05H)
6 INVERT_B 0 5 CPEN 1 4 PDN 1 3 MUTEC A = B 0 2 FREEZE 0 1 MCLK Divide 0 0 Reserved 0
7 INVERT_A 0
INVERT_A (Invert Channel A) Default = `0'. 0 - Disabled 1 - Enabled INVERT_B (Invert Channel B) Default = `0'. 0 - Disabled 1 - Enabled CPEN (Control Port Enable) Default = `0' 0 - Disabled (Stand-Alone Mode) 1 - Enabled (Control Port Mode) PDN (Power-Down) Default ='1'. 0 - Disabled 1 - Enabled MUTEC A=B Default = `0'. 0 - Disabled 1 - Enabled FREEZE Default = 0. 0 - Disabled 1 - Enabled MCLK Divide Default = 0. 0 - Disabled 1 - Enabled
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4.
4.1
REGISTER DESCRIPTION
MODE CONTROL 1 - ADDRESS 01H
7 AMUTE 6 DIF2 5 DIF1 4 DIF0 3 DEM1 2 DEM0 1 FM1 0 FM0
** All register access is R/W in I2C mode and write only in SPI mode **
4.1.1
Auto-Mute (Bit 7)
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. (However, Auto-Mute detection and muting can become dependent on either channel if the Mute A = B function is enabled.) The common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute period. The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
4.1.2
Digital Interface Formats (Bits 6:4)
Function:
PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Table 2 and Figures 7-24. DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional Mode registers must be set to DSD Mode. See Table 1 (PCM Modes) See Table 2 (DSD Mode)
4.1.3
De-Emphasis Control (Bits 3:2)
Function:
Implementation of the standard 15 s/50 s digital de-emphasis filter response, Figure 13, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is available only in Single-Speed Mode. See Table 3
4.1.4
Functional Mode (Bits 1:0)
Function:
Selects the required range of input sample rates or DSD Mode. See Table 4
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4.2 VOLUME AND MIXING CONTROL (ADDRESS 02H)
7 A=B 6 Soft 5 Zero Cross 4 ATAPI4 3 ATAPI3 2 ATAPI2 1 ATAPI1 0 ATAPI0
4.2.1
Channel A Volume = Channel B Volume (Bit 7)
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
4.2.2
Soft Ramp or Zero Cross Enable (Bits 6:5)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 5
4.2.3
ATAPI Channel Mixing and Muting (Bits 4:0)
Function:
The CS4391A implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 6
4.3
CHANNEL A VOLUME CONTROL - ADDRESS 03H
See Section 4.4 Channel B Volume Control - Address 04h
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4.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H
7 MUTE 6 VOL6 5 VOL5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0
4.4.1
Mute (Bit 7)
Function:
The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.
4.4.2
Volume Control (Bits 6:0)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -119 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less than -119 dB are equivalent to enabling the Mute bit.
4.5
MODE CONTROL 2 - ADDRESS 05H
6 INVERT_B 5 CPEN 4 PDN 3 MUTEC A = B 2 FREEZE 1 MCLK Divide 0 Reserved
7 INVERT_A
4.5.1
Invert Signal Polarity (Bits 7:6)
Function:
When set, this bit inverts the signal polarity.
4.5.2
Control Port Enable (Bit 5)
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean and click free power-up, the user should write 30h to register 5 within 10 ms following the release of Reset.
4.5.3
Power Down (Bit 4)
Function:
The device will enter a low-power state whenever this function is activated. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when the device is in power-down.
4.5.4
AMUTEC = BMUTEC (Bit 3)
Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally connected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
20
DS600PP3
CS4391A
4.5.5 Freeze (Bit 2)
Function:
This function allows modifications to the registers without the changes being taking effect until Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the Freeze Bit, make all register changes, then Disable the Freeze bit.
4.5.6
Master Clock Divide (Bit 1)
Function:
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is required to access the higher Master Clock rates as shown in Table 9.
DS600PP3
21
CS4391A
5. PIN DESCRIPTION - PCM DATA MODE
Reset RST Logic Voltage VL Serial Data SDATA Serial Clock SCLK Left/Right Clock LRCK Master Clock MCLK See Description M3 See Description (SCL/CCLK) M2 See Description (SDA/CDIN) M1 See Description (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+
Channel A Mute Control Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Channel B Mute Control Common Mode Voltage Positive Voltage Reference
Reset - RST Pin 1, Input Function: Hardware Mode: The device enters a low power mode and the internal state machine is reset to the default setting when low. When high, the device becomes operational. Control Port Mode: The device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port can not be accessed when reset is low. The Control Port Enable Bit must also be enabled after a device reset. RST is required to remain low until the power supplies and clocks are applied and stable. Interface Power - VL Pin 2, Input Function: Digital interface power supply. The voltage on this pin determines the logic level high threshold for the digital inputs. Serial Audio Data - SDATA Pin 3, Input Function: Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode Pins in Hardware Mode. The options are detailed in Figures 7-24.
22
DS600PP3
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Serial Clock - SCLK Pin 4, Input Function: Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode pins in Hardware Mode. The options are detailed in Figures 7-24. Left / Right Clock - LRCK Pin 5, Input Function: The Left / Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode pins in Stand-alone Mode. The options are detailed in Figures 7-24. Master Clock - MCLK Pin 6, Input Function: The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Single Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or 64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Tables 8-10 illustrate the standard audio sample rates and the required master clock frequencies. Note: These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled. Mode Select - M3, M2, M1 and M0 (Stand-alone Mode) Pins 7, 8, 9 and 10 Inputs Function: The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15.
Mode Select - M3 (Control Port Mode) Pin 7, Input Function: The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground.
DS600PP3
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CS4391A
Serial Control Interface Clock - SCL/CCLK (Control Port Mode) Pin 8, Input Function: Clocks the serial control data into or from SDA/CDIN. Serial Control Data I/O - SDA/CDIN (Control Port Mode) Pin 9, Input/Output Function: In I2C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Address Bit / Chip Select - AD0 / CS (Control Port Mode) Pin 10, Input Function: In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle. Positive Voltage Reference - FILT+ Pin 11, Output Function: Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figures 5 and 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Common Mode Voltage - CMOUT Pin 12, Output Function: Filter connection for internal common mode reference voltage, typically 50% of VA. Capacitors must be connected from CMOUT to analog ground, as shown in Figures 5 and 6. CMOUT is not intended to supply external current. CMOUT has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Channel A and Channel B Mute Control - AMUTEC and BMUTEC Pins 13 and 20, Outputs Function: The Mute Control pins go high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. These pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
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Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTAPins 14, 15 and 18, 19, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table. Analog Ground - AGND Pin 16, Input Function: Analog ground reference. Analog Power - VA Pin 17, Input Function: Analog power supply.
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CS4391A
6. PIN DESCRIPTION - DSD MODE
Reset RST Logic Voltage VL Channel A Data DSD_A Channel B Data DSD_B DSD Mode Select DSD_MODE Master Clock MCLK DSD Serial Clock DSD_SCLK Refer to PCM Mode (SCL/CCLK) M2 Refer to PCM Mode (SDA/CDIN) M1 Refer to PCM Mode (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Refer to PCM Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode
DSD Audio Data - DSD_A and DSD_B Pins 3 and 4, Inputs Function: Direct Stream Digital audio data is clocked into DSD_A and DSD_B via the DSD serial clock. DSD Mode - DSD_Mode Pin 5, Input Function: This pin must be set to a logic `1' and M0-M2 must be properly set to access the DSD Mode in Hardware Mode. Refer to Table 2. In Control Port Mode, this pin must be set to a logic `1' and the Control Registers must be properly set to access the DSD Mode. Refer to register descriptions. Master Clock - MCLK Pin 6, Input Function: The master clock frequency must be either 4x, 6x, 8x or 12x the DSD data rate for 64x oversampled DSD data or 2x, 3x, 4x or 6x the DSD data rate for 128x oversampled DSD data. DSD Serial Clock - DSD_SCLK Pin 7, Input Function: Clocks the individual bits of the DSD audio data into the DSD_A and DSD_B pins.
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DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIFO 0 1 0 1 0 1 0 1
DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Right Justified, 24-bit Right Justified, 20-bit Right Justified, 18-bit Reserved Reserved Data Data Data Data
Table 1. Digital Interface Formats - PCM Modes
DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIFO 0 1 0 1 0 1 0 1
DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 2. Digital Interface Formats - DSD Mode
DEM1 0 0 1 1
DEMO 0 1 0 1
DESCRIPTION Disabled 44.1 kHz de-emphasis 48 kHz de-emphasis 32 kHz de-emphasis
Table 3. De-Emphasis Mode Selection
FM1 0 0 1 1
FM0 0 1 0 1
MODE Single-Speed Mode (4 to 50 kHz sample rates) Double-Speed Mode (50 to 100 kHz sample rates) Quad-Speed Mode (100 to 200 kHz sample rates) Direct Stream Digital Mode Table 4. Functional Mode Selection
SOFT 0 0 1 1
ZERO 0 1 0 1
Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled
Table 5. Soft Cross or Zero Cross Mode Selection
DS600PP3
27
CS4391A
ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2]
AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
Table 6. ATAPI Decode Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB
Table 7. Digital Volume Control
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Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled. Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 See Note 1024x 32.7680 45.1584 49.1520
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
Sample Rate (kHz) 64 88.2 96
128x 8.1920 11.2896 12.2880
MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760
384x 24.5760 33.8688 36.8640
See Note 512x 32.7680 45.1584 49.1520
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 176.4 192 64x 11.2896 12.2880 MCLK (MHz) 96x 128x 16.9344 22.5792 18.4320 24.5760 192x 33.8688 36.8640 See Note 256x 45.1584 49.1520
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies M3 0 0 0 0 M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data FORMAT 0 1 2 3 FIGURE 7 8 9 10
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
M3 0 0
M2 (DEM) 0 1
DESCRIPTION No De-Emphasis De-Emphasis Enabled
FIGURE 13 13
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
M3 1 1 1 1
M2 0 0 0 0
M1 0 0 1 1
M0 0 1 0 1
DESCRIPTION Left Justified up to 24-bit data I2S up to 24-bit data Right Justified 16-bit data Right Justified 24-bit data
FORMAT 0 1 2 3
FIGURE 7 8 9 10
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
DS600PP3
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CS4391A
M3 1 1 1 1
M2 1 1 1 1
M1 0 0 1 1
M0 0 1 0 1
DESCRIPTION Left Justified up to 24-bit data I2S up to 24-bit data Right Justified 16-bit data Right Justified 24-bit data
FORMAT 0 1 2 3
FIGURE 7 8 9 10
Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options
DSD_Mode 1 1 1 1 1 1 1 1
M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options
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LRC K SC L K
L eft C ha n n el
R igh t C ha n n el
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 7. Format 0, Left Justified up to 24-Bit Data
LRC K SC L K
L eft C ha n n el
R igh t C ha n n el
SDATA
MS B -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LS B
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 8. Format 1, I2S up to 24-Bit Data
LRCK
Le ft C h a n ne l
R ig h t C h a nn e l
SCLK
SDATA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
3 2 clo cks
Figure 9. Format 2, Right Justified 16-Bit Data
LRCK
L e ft C h a n ne l
R ig h t C h a n ne l
SCLK
SDATA
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
3 2 clo cks
Figure 10. Format 3, Right Justified 24-Bit Data
DS600PP3
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CS4391A
LR C K
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
SDATA
1
0
1 9 1 8 17 16 15 14 1 3 1 2 11 10 9
8
7
6
5
4
3
2
1
0
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
3 2 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) Figure 11. Format cloc ks
LR CK
L eft C h a nn e l
R ig h t C h a n ne l
SCLK
SDATA
1
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure 12. Format 5, 32 clocks Justified 18-Bit Data. (Available in Control Port Mode only) Right
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 13. De-Emphasis Curve
Left Channel Audio Data
A Channel Volume Control
MUTE
AoutA
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutB
Figure 14. ATAPI Block Diagram 32 DS600PP3
CS4391A
7. APPLICATIONS 7.1 Recommended Power-up Sequence for Hardware Mode
lowing the release of RST. 4) The desired register settings can be loaded while keeping the PDN bit set to 1. 5) Set the PDN bit to 0 which will initiate the power-up sequence which requires approximately 10 S.
1) Hold RST low until the power supplies, master, and left/right clocks are stable. 2) Bring RST high.
7.2
Recommended Power-up Sequence and Access to Control Port Mode
7.3
Analog Output and Filtering
1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and CMOUT will remain low. 2) Bring RST high. The device will remain in a low power state with CMOUT low and the control port is accessible. 3) Write 30h to register 5 within 10 ms cycles fol-
The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the secondorder Butterworth filter and differential to singleended converter which was implemented on the CS4391A evaluation board, CDB4391A. The CS4391A filter, as seen in Figure 14, is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
R28 C7 2700PF COG
GND
5.62K
C6
560PF COG
VCC
C49 .1UF V+ C42
AOUTA8
10UF 10UF
R24 R26
5.62K 5.62K C14 2700PF COG
GND
R17 R18 R15 5.62K
1.18K 1.18K
U11 GND
1
2
J3 CON_RCA_RA R20 560 R5 47K
HDR1X2 HDR8 1 2 1 2 3 4 NC
C43
AOUTA+
3
+ C5 560PF COG
GND VEE
MC33078D
4
AOUTA
V-
C48 .1UF
GND
GND
GND
GND
VA+3/+5
2
1
MMUN2111LT1 Q3
3
Q1 2SC2878 R25 2K
3
2
3
AMUTEC
1
Q4 MMUN2211LT1
2
1
GND GND
Figure 15. CS4391A Output Filter
DS600PP3
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CS4391A
8. CONTROL PORT INTERFACE
The control port is used to load all the internal settings of the CS4391A. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4391A operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VA or AGND. If the CS4391A ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. The control port registers are write-only in SPI mode. INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
8.2
I2C Mode
8.1
SPI Mode
In SPI mode, CS is the CS4391A chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. Figure 16 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See Table 16. The CS4391A has MAP auto increment capability, enabled by the INCR bit in the MAP register. If
In I2C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 3. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the CS4391A the LSB of the chip address field, which is the first byte sent to the CS4391A, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. The CS4391A has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. For more information on I2C, please see "The I2CBus Specification: Version 2.0", listed in the References section.
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7 INCR 0
6 Reserved 0
5 Reserved 0
4 Reserved 0
3 Reserved 0
2 MAP2 0
1 MAP1 0
0 MAP0 0
INCR (Auto MAP Increment Enable) Default = `0'. 0 - Disabled 1 - Enabled MAP0-2 (Memory Address Pointer) Default = `000'. Table 16. Memory Address Pointer (MAP)
CS CCLK C H IP ADDRESS C DIN
0 01 00 0 0
R/W
MAP
MSB
DATA
LS B
b yte 1 M AP = M e m ory Ad d re ss P o in te r
b yte n
Figure 16. Control Port Timing, SPI mode
N ote 1 SDA
0 010 00 ADDR AD 0 R /W ACK DATA 1 -8 ACK D AT A 1-8 AC K
SCL S ta rt Stop
N ote: If o pera tion is a w rite, th is byte co ntain s the M em ory A dd re ss P o inter, M A P .
Figure 17. Control Port Timing, I2C Mode
DS600PP3
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CS4391A
0.25 0.2 0.15 0.1 Amplitude dB 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
Figure 18. Single-Speed Frequency Response
Figure 19. Single-Speed Transition Band
Figure 20. Single-Speed Transition Band
Figure 21. Single-Speed Stopband Rejection
0.25 0.2 0.15 0.1 Amplitude dB 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
Figure 22. Double-Speed Frequency Response
Figure 23. Double-Speed Transition Band
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DS600PP3
CS4391A
Figure 24. Double-Speed Transition Band
Figure 25. Double-Speed Stopband Rejection
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CS4391A
9. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
10.REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4391A Evaluation Board Datasheet 3. "The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
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11.PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4
MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8
MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS600PP3
39
CS4391A
PACKAGE DIMENSIONS(cont.).
20L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1b
c D
L A
SEATING PLANE e A1
DIM A A1 b C D E e H L
MIN 0.093 0.004 0.013 0.009 0.496 0.291 0.040 0.394 0.016 0
INCHES NOM 0.098 0.008 0.017 0.011 0.504 0.295 0.050 0.407 0.025 4
MAX 0.104 0.012 0.020 0.013 0.512 0.299 0.060 0.419 0.050 8 JEDEC #: MS-013
MIN 2.35 0.10 0.33 0.23 12.60 7.40 1.02 10.00 0.40 0
MILLIMETERS NOM 2.50 0.20 0.43 0.28 12.80 7.50 1.27 10.34 0.64 4
MAX 2.65 0.30 0.51 0.32 13.00 7.60 1.52 10.65 1.27 8
Controlling Dimension is Millimeters
40
DS600PP3

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